Design and simulation of a RISC-V dual-core lockstep for fault tolerant systems

Abstract

Embedded processors are increasingly being used in every industry and consumer segment, including critical-safety applications. The critical parameter of the processors, previously performance, was replaced by the need to guarantee the reliability of the system. This paradigm shift leads to the use of techniques for the development of fault-tolerant devices. Aerospace and, more recently, automotive applications are more susceptible to failures caused by the incidence of radiation in the integrated circuits that make up the systems, due to the reduction in the size of the transistor and the increase in the complexity of the devices. In this context, the use of FPGA (Field Programmable Gate Array) is attractive to the industry for implementing secure systems, due to the versatility and customization of designs on the devices. However, radiation-resistant FPGA has a high acquisition cost, in addition to being developed with legacy integrated circuit technology if compared with FPGA COTS (Commercial Off the Shelf). To increase the reliability and security of systems implemented in FPGA COTS, this work implements a dual-core Lockstep (DCLS) system for open-source processors architecture RISC-V, using the RI5CY core. We believe that this is the first work that implements a DCLS architecture with RISC-V cores, performs a fault injection routine via software, and evaluates its hardware and software overhead. A fault injection framework is proposed and implemented using an open-source simulation tool. The system is implemented in FPGA and the hardware overhead is small, reaching just over 5.18% compared to a single RI5CY core. The maximum clock frequency reduction achieved by the system implemented in a Xilinx Kintex KC705 reached 18.5%. Fault injection results indicate that the system is effective in detecting faults at the outputs of colors, where all visible errors were detected. Fault injection tests shows the discrepancy between transient and permanent fault injection in the Design Under Test due to the difference between visible errors.